Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
نویسندگان
چکیده
منابع مشابه
Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation
Clock driver suffers from delay variation due to manufacturing and environmental variabilities as well as combinational cells. The delay variation causes clock skew and jitter, and varies both setup and hold timing margins. This paper presents a timing verification method that takes into consideration delay variation inside a clock network due to both manufacturing variability and dynamic power...
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A robust physical design of 3D-IC requires investigation on through-silicon-via (TSV). The large temperature and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electrical-thermal-mechanical delay model...
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Modern computing system applications or workloads can bring significant non-uniform temperature gradient on-chip, and hence can cause significant temperature uncertainty during clock-tree synthesis. Existing designs of clock-trees have to assume a given time-invariant worst-case temperature map but cannot deal with a set of temperature maps under a set of workloads. For robust clock-tree synthe...
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ژورنال
عنوان ژورنال: ACM Transactions on Design Automation of Electronic Systems
سال: 2014
ISSN: 1084-4309,1557-7309
DOI: 10.1145/2651401